1. Field of the Invention
This invention relates to an address comparator. More particularly, this invention relates to an address comparator for comparing a write address value and a read address value in an elastic store circuit where a write address counter and a read address counter are provided independently and writing and reading of data can be performed independently and simultaneously.
2. Description of the Prior Art
The LSI technology is recently remarkably developed and introduction of LSI makes it possible to manufacture small-sized digital communication apparatus at low cost. Particularly, synchronous multiplex converting apparatus in a digital network serves to multiplex and insert a lower group of signals into a higher group of signals or to multidrop a higher group of signals to a lower group of signals. In such a digital network, there is provided an elastic store circuit having a function of absorbing a jitter in the transmission line and a change in delay and a function of synchronizing with the station frame phase.
Such an elastic store circuit has been already disclosed in Electric Communication Journal (September, 1980, Vol. J63-CNo. 9) by Hideki Fukuda et al. and in connection with an elastic store circuit, Japanese patent applications were filed (Japanese Patent Laid Open Gazette No. 53935/1980 and Japanese Patent Laid Open Gazette No. 64934/1979).
FIG. 1 is a schematic block diagram of an elastic store circuit. First, referring to FIG. 1, a construction and an operation of an elastic store circuit will be described. A write clock signal is supplied to a write address counter 1. The write address counter 1 counts a write clock signal and supplies the count output as a write address signal to a write address decoder 2 and an address comparator 4. The write address decoder 2 decodes the write address signal and supplies the write address decode signal to a store cell 3. Then, data is written in an address designated by the write address decode signal of the store cell 3.
On the other hand, to a read address counter 5, a read clock signal different from the write clock signal is supplied. The read address counter 5 counts the read clock signal and supplies the count output as a read address signal to a read address decoder 6 and the address comparator 4. The read address decoder 6 decodes the read address signal and supplies the read address decode signal to the store cell 3. Thus, data is read out from the store cell 3 of the address designated by the read address decode signal.
As described above, in the elastic store circuit, the write signal and the clock signal are independently applied. As a result, the elastic store circuit has advantageous features that change in phase at the time of writing data can be absorbed, an output without phase change can be obtained at the time of reading data and the writing speed and the reading speed can be changed and data can be multiplexed.
However, if in such an elastic store circuit, the output address values of the write address counter 1 and the read address counter 5 become near each other, there is a fear of erroneous operation such as rewriting of data in the address where reading is not completed or rereading of data in the address where the old data which should be already read out remains. For the purpose of preventing such erroneous operation, the address value of the write address counter 1 and the address value of the read counter 5 are compared by the address comparator 4 so that an alarm is issued when the difference between the address values of the write address counter 1 and the read address counter 5 is smaller than a predetermined value.
FIG. 2 is a block diagram of the address comparator shown in FIG. 1. In FIG. 2, the address comparator 4 comprises a write reset timing signal detecting portion 7, a read reset timing signal detecting portion 8, a timing difference setting portion 9 and a timing comparing portion 11. The write reset timing signal detecting portion 7 receives the count output of the write address counter 1 and the read reset timing signal detecting portion 8 receives the count output of the read address counter 5. The write reset timing signal detecting portion 7 detects timing for resetting the write address counter 1 by a write address counter reset signal and the read reset timing signal detecting portion 8 detects timing for resetting the read address counter 5 by a read address counter reset signal.
The detection signal of the write reset timing signal detecting portion 7 and the detection signal of the read reset timing signal detecting portion 8 are supplied to the timing comparing portion 11. To the timing difference setting portion 9, a setting signal is supplied from the exterior and an output of the timing difference setting portion 9 is supplied to the timing comparing portion 11. The timing comparing portion 11 provides an output signal when the difference between the write reset timing detected by the write reset timing signal detecting portion 7 and the read reset timing detected by the read reset timing signal detecting portion 8 is smaller than the value set by the timing difference setting portion 9.
Now, an operation of the address comparator 4 will be specifically described. Assuming that the storage capacity of the store cell 3 shown in FIG. 1 has N address positions (N being positive integer), the write address counter 1 and the read address counter 2 are also formed by modulo-N counters. When the write clock signal is supplied to the write address counter 1 by one pulse, the count output thereof increases by one. Similarly, when the read clock signal is supplied to the read address counter 5 by one pulse, the count output increases by one. Then, when the write address counter reset signal or the read address counter reset signal is applied in the state in which the count value of the write address counter 1 and that of the read address counter 5 are respectively N-1, these counters 1 and 5 are reset and the count values thereof return to zero. On the other hand, at the time of initialization, the write address counter 1 is initialized by the write address counter reset signal and the read address counter 5 is initialized by the read address counter reset signal so that the initial count values thereof are respectively zero.
The cycle of the write clock signal is generally not equal to the cycle of the read clock signal and besides, there is a change in the cycle of the write clock signal itself. Accordingly, the difference between the output address value of the write address counter 1 and the output address value of the read address counter 5 is generally varied at all times. If this difference becomes smaller than the singal set in the timing difference setting portion 9 from the exterior, the timing comparing portion 11 provides an output signal to issue an alarm.
More specifically, the write reset timing signal detecting portion 7 detects the reset timing for the write address counter 1 and the read reset timing signal detecting portion 9 detects the reset timing for the read address counter 1 whereby a timing difference therebetween is detected by the timing comparing portion 11. If the timing difference detected by the timing comparing portion 11 is smaller than the value set in the timing difference setting portion 9, an output singal is provided to give an alarm.
The set value of the timing difference setting portion 9 is set by the user of this apparatus from the exterior. The value to be set is usually determined by selecting one value out of four values predetermined in view of the characteristics of the write clock signal, the read clock signal and the like.
A conventional address comparator constricted as described above involves no problem in so far as the cycle of the write clock signal and that of the read clock signal are coincident. However, if the cycle of the write clock signal and that of the read clock signal are different as in the case where the elastic store circuit is utilized for speed selection, it sometimes happens that the write address by the write clock signal and the read address by the read clock signal come near. Consequently, the above described error in writing or reading of data might occur. For the purpose of avoiding such error, it is necessary to control the timing of reading and writing by using a controller or the like.
In addition, although in a conventional elastic store circuit, the timing difference between the write reset timing signal and the read reset timing signal is detected, a timing difference between a write address and a read address at the time other than that of resetting the write address counter 1 and the read address counter 5 cannot be known. If a write address and a read address approach each other as a result of a difference caused between the cycles of the clock signals, such approach cannot be detected.